Time of arrival of direct path signal is classically based on correlation process. The correlation process consists in multiplying and accumulating received signal (combination of N PRN) with a local PRN after down-converting received PRN signal into baseband. For reasons of complexity and resources the local signal is an ideal NRZ waveform without modelling of the filter effect.  That limits the number of bits needed to store the accumulation value as the FPGA blocs required to multiply the received signal with the local signal. The impact of multipath on time of arrival measurement in harsh indoor environment implies to have some flexibility in correlator position and to be able to have a high resolution of the correlation function (very narrow spaced correlator).

The tracking process could be separated in two main actions. First, a code/carrier tracking error is computed based on correlation information (alternatively based on compressed signal). Then, this instantaneous error is filtered before correcting the local code/carrier generation. The loop filter can be optimised for the considered application (example: pedestrian) but the main work is on the estimation of the tracking error of the LOS signal. The objective is to fight multipath to get accuracies close to one meter. First, classic discriminator (narrow correlator and double delta correlator mainly) are tested with a correlator spacing as narrow as possible to remove a maximum of multipath bias. The high SNR (Signal to Noise Ratio) and high receiver bandwidth of the receiver platform will allow tightening the correlator more than in a GNSS system. If the multipath mitigation of these technique after tightened at the maximum the correlator spacing is still not suitable to reach such a level of performance, then the implementation of other techniques will be considered. Finally, as each PRN suffers more or less from multipath or other degradations, vector tracking will be considered to help poor PRN tracking with other PRN tracking by the mean of the predicted position and clock bias.

In order to increase multipath robustness it is planned to use faster chip rates, from 1 Mchip/s (E1) to 5 Mchip/s (E6).